The present invention generally relates to designing of electronic devices and more particularly to a designing method of an electronic device produced by a process that includes a CMP (chemical mechanical polishing) process and a fabrication method of an electronic device that uses such a designing method. In the present invention, an electronic device includes semiconductor devices, thin film magnetic heads, CCD devices, laser diodes, and the like.
Electronic devices such as a semiconductor device or a thin film magnetic head generally has a layered structure in which plural thin films are stacked and produced generally by a process that includes a planarization process conducted by a CMP process.
In the fabrication of a semiconductor integrated circuit that includes a MOS transistor, for example, it is practiced to form an STI (shallow trench isolation) structure by the steps of forming a trench on the surface of a silicon substrate, filling the trench by an insulation film, and polishing out excessive insulation film from the surface of the silicon substrate by a CMP process.
FIGS. 1A-1E show a typical conventional process of forming an STI structure.
Referring to FIG. 1A, a silicon oxide film 12 is formed on a surface of a silicon substrate 11 by a thermal oxidation processing, and a silicon nitride film 13 is formed further thereon by a sputtering process, CVD (chemical vapor deposition) process, and the like.
Next, in the step of FIG. 1B, the silicon nitride film 13 is patterned in a predetermined region where the device isolation region is to be formed, and the silicon oxide film 12 and the underlying silicon substrate 11 are patterned while using the silicon nitride pattern thus formed as a mask to form a trench 14 in the silicon substrate 11.
Next, in the step of FIG. 1C, a thermal oxide film 15 is formed on the inner wall surface of the trench 14, and the trench 14 thus formed with the thermal oxide film 15 is filled with an insulation film 16 by depositing the same on the silicon substrate 11 by a high density plasma CVD process that may use SiH4 and O2 for the source gas. Further, in the step of FIG. 1D, the excessive insulation film 16 on the silicon substrate 11 is removed by a polishing process conducted by a CMP process. Thereby, the nitride film pattern 13 functions as a polishing stopper.
Further, in the step of FIG. 1E, the silicon nitride film 13 and the oxide film 12 are removed by respective wet etching processes, and there is formed an STI device isolation region 17 in which the device isolation trench 14 is filled with the silicon oxide film 16 is obtained so as to define a device region 18 on the silicon substrate 11.
Meanwhile, it is known that the flatness of the silicon substrate 11 thus polished by a CMP process changes depending on the layout of the device elements formed on the silicon substrate 11.
For example, in the case in which the device regions 18 are sparse on the substrate and hence there extends a wide device isolation region 17 between adjacent device regions 18 in FIG. 1E, the insulation film 16 has to fill the wide device isolation trench 14 having a large volume in the step of FIG. 1C, and thus, the film thickness on the silicon substrate 11 is tend to be reduced. In the case the device regions 18 are formed densely on the substrate 11, on the other hand, the device isolation trenches 14 have a reduced width, and thus, the insulation film 16 is deposited on the silicon substrate 11 with increased thickness.
Thus, in the case of polishing a wafer in which the device regions are formed with a density that changes depending on the location on the wafer by a CMP process, there is a possibility that polishing becomes excessive in the regions where the insulation film 16 has a small thickness and insufficient in the regions where the insulation film 16 has a large thickness.
FIG. 2 shows an example of a silicon substrate 30 in which the density of the device region varies depending on the location of the substrate.
Referring to FIG. 2, it can be seen that there are formed device regions 31 having a size of 500 μm at each edge repeatedly in a first region A of the substrate for the overall length of about 1 mm, and device isolation regions 32 having a width of about 1 μm are formed between adjacent device regions 31. On the other hand, as shown in enlarged view of FIG. 2, there is formed a second region B on the substrate adjacent to the second region A in such a manner that square regions 33 each having a size of 0.5 μm for each edge are formed over the length of about 1000 μm, such that each square region 33 is separated from an adjacent square region 33 by a device isolation region 33 having a size of 1 μm.
FIG. 3 is a cross-sectional diagram of the substrate 30 of FIG. 2 in which the device isolation trench in the substrate 30 is filled with a silicon oxide film 35 corresponding to the insulation film 16 according to the process steps of FIGS. 1A-1E in the state in which the excessive silicon oxide film 35 on the substrate 31 is removed by a CMP process.
Referring to FIG. 3, there occurs a thick deposition of the silicon oxide film 35 (thickness=t1) on the device region 31 in the region A where the device regions are formed with large density, as represented by a broken line. In such a region, there remains a silicon oxide film residue 35X after the CMP process conducted on a silicon nitride film corresponding to the silicon nitride film 13 noted before, and thus, there appears a state of insufficient polishing.
In the region B where the density of the device region is small, on the other hand, there occurs a dip (erosion) in the silicon oxide film 35 deposited with a reduced film thickness (thickness=t2, t2<t1) as represented by a broken line, and there appears a state of excessive polishing.
In this way, there can be caused both a region of insufficient polishing and a region of excessive polishing on a single substrate when there exist a region in which the device regions are formed densely and a region in which the device regions are formed sparsely. It should be noted that, once such a state is caused, it cannot be resolved even when optimization of polishing rate is made by way of optimization of polishing time, and the like.
In order to solve this problem and to secure uniformity of polishing process, there is a proposal to add dummy device regions to the part of the substrate surface where the device regions 18 are formed with sparse interval, such that the density of the device regions is maintained uniformly all over the entire substrate surface.
For example, Japanese Laid-Open Patent Application 2001-7114 proposes the technology of dividing the silicon substrate surface into sub-regions and imposing a limitation on such sub-regions with regard to a coverage ratio, which is the proportion of the area of the sub-region occupied by the device regions, for ensuring uniform polishing.
FIG. 4 shows an example of such sub-regions formed on a silicon substrate surface.
Referring to FIG. 4, each of the sub-regions has a size of 100 μm×100 μm in the illustrated example, and there are formed sub-regions 51 represented without hatching and sub-regions 52 represented with hatching. Here, the sub-regions 51 have a coverage ratio of 80%, while the sub-regions 52 have a coverage ratio of 20%. It will be noted that the sub-regions 51 and the sub-regions 52 are disposed at random on the substrate. As noted above, the coverage ratio is defined for each sub-region as the total area of the device regions in a sub-region divided by the area of that sub-region.
In this conventional art, it becomes possible to realize uniform polishing in the CMP process of FIG. 1D, provided that the sub-regions of different coverage ratios are distributed at random on the substrate. On the other hand, in the case there exists a deviation in the pattern of the sub-regions on the substrate such that the sub-region of particular coverage ratio cluster together in a particular part of the substrate, for example, the problem of non-uniform polishing in the CMP process cannot be avoided with the technology of this prior art.
On the other hand, the inventor of the present invention has proposed, in the Japanese Laid-Open Patent Application 2003-347406, a technology capable of ensuring uniform polishing in the CMP process by: dividing the substrate surface into small sub-regions shown in FIG. 5; conducting layout of a semiconductor device such that the coverage ratio falls in a particular range for each of the small sub-regions; re-dividing the substrate surface into large sub-regions 53 and 54 having a size of 300 μm or more for each edge as shown in FIG. 6; and modifying the layout such that the coverage area of the device regions falls in a predetermined range in each of the large sub-regions 53 and 54. In the examples of FIGS. 5 and 6, it should be noted that the small sub-regions 51 and 52 have a size of 250 μm for each edge.
Thus, by modifying the layout such that the coverage ratio of the device region falls in a predetermined area also in such large sub-regions, non-uniform distribution of the device region in the large sub-regions 56 and 57 such as the one shown in FIG. 7 is eliminated, and uniform polishing is ensured in the CMP process of FIG. 1C.